Last week we began disclosing very promising initial device results from our ferroelectric memory technology research work to our contacts in the commercial microelectronics world. The well-connected Peter Clarke picked up this activity for an article at eeNews Analog (Picture, left). This blog post adds additional background on ferroelectric memory and why we are excited about the potential of this technology.
First, you will note that our public website focuses on a 2nd memory technology, Correlated Electron RAM (CeRAM). We continue to make progress on CeRAM in our research lab in Colorado Springs as well as at Imec, and have expanded into four US government funded research awards. But today, we would like to introduce you to Ferroelectric memory.
Ferroelectric memory was a highly successful memory technology after its development in the 1980s by Samsung, SK Hynix, Sony, Texas Instruments, Fujitsu, Toshiba, Cypress, IBM, Rohm, Panasonic and others. Worldwide sales reached $235B in 2005, with Panasonic, TI, Cypress, Rohm and Fujitsu continuing to ship product in a wide variety of applications including IoT, health care products, etc., including billions of smart cards, ferroelectric memory has shipped more units than all other emerging memory technologies combined. The technology has a low cost of manufacture, operates at significantly lower voltage/power than flash memory, is much faster than flash memory, exhibits an extremely high endurance (a key challenge for all emerging memory technologies, the number of times you can write information), and is innately rad-hard. Comparisons to flash memory are the most direct because, of the three main incumbent memory technologies, flash is the only non-volatile technology. Both SRAM and DRAM lose their information when the power is turned off. DRAM forgets its information in much less than one second, even when the power is on, and must be “refreshed,” a process that creates most of the power consumption of DRAM. The non-volatile ferroelectric memories do not need to be refreshed, and this promise of significant power reduction as a DRAM replacement technology drove much of the early R&D investment.
These ferroelectric memory technologies had an Achille’s heel, though. They required a high temperature manufacturing process with an anneal step at > 500 degrees Celsius. This was not an issue in older wafer process technologies (CMOS “Nodes”), down to the 130nm process node. However, more advanced CMOS nodes require process temperatures to be < 400 C, ending the Moore’s Law scaling for ferroelectric memory. Without the need for high-temperature processing, flash memory continued to scale to 28nm providing a significant cost and density advantage over ferroelectric memories built at 130nm.
In collaboration with our sister company Symetrix, the pioneers in original ferroelectric memory technology, we have created a ferroelectric memory device that breaks through this critical 400C limit while maintaining the high endurance, retention, and performance of traditional ferroelectric memories. This breakthrough will extend the many attractive characteristics of ferroelectric technology to advanced process nodes. SNAP Ferro will scale well beyond where flash memory stopped, and SNAP Ferro can potentially follow the successful 3D NAND path of flash memory that today provides the lowest cost, highest density memory products available. With renewed scalability, SNAP Ferro can take on the DRAM applications that originally drove a lot of this technology's excitement. Additionally, SNAP Ferro can be integrated into a Field Effect Transistor. Utilizing the high endurance of ferroelectric switches, a SNAP Ferro “FET” could create entirely new microelectronic computing paradigms, especially in low power IoT applications, by bringing non-volatility to logic devices for the first time.
SNAP Ferro should not be confused with research into “induced” ferroelectric materials that began with a discovery by NaMLab Dresden. The investigation of “induced” ferroelectricity has spread widely in the R&D community over the last 11 years. At the recent IEEE VLSI Technology Symposium conference (June 2021), ferroelectric memory technology R&D was presented by researchers at universities spanning from the U.S. (Purdue, Notre Dame), Japan, Taiwan, China, Belgium and Singapore, and from many established semiconductor companies including GlobalFoundries, Samsung, TSMC, Sony and NXP. Additionally, many research consortiums presented work, including Japan’s AIST, Taiwan’s TRSI, and Belgium’s IMEC. The reason that ferroelectric memory technology filled not one, not two, but three full sessions at the conference (and was additionally featured in many other sessions of the conference), by such a wide array of global researchers, more than a decade after its discovery, is a combination of (a) the value that is seen in finding a way to scale ferroelectric memory to smaller process nodes and (b) the difficulty of chasing a solution based on “induced” ferroelectricity. Inducing ferroelectricity in a material that is not innately ferroelectric requires operation at high electric fields and brings in the challenge of film metastability which degrades the reliability of the devices (endurance, retention, etc.) and presents new difficulties in process control and variability. Therefore, we cannot project if/when a research breakthrough will solve the challenges that are preventing this technology from reaching commercial production. It was precisely our concern with this type of approach that led to what we believe is a better path for ferroelectric memory. The table below summarizes key technology differences.
We are very excited about the commercial prospects of SNAP Ferro as it combines proven technology with our innovation to create a memory technology that has superior characteristics and scalability. We will be optimizing our technology beyond these initial results and will disclose the details of the technology to interested parties in August. At that point, we will be seeking partnerships to perform fab-level development that is beyond the capabilities of our R&D lab.